a. The Field of the Invention
This invention relates to the field of integrated circuit manufacturing. In particular, the invention relates to the concepts and implementation techniques to make fast and efficient integrated circuit layout design rule checking possible.
b. Description of Related Art
In designing an integrated circuit (IC), engineers typically rely upon computer simulation tools to help create a circuit schematic design consisting of individual devices coupled together to perform a certain function. To actually fabricate this circuit in a semiconductor substrate the circuit must be translated into a physical representation, or layout, which itself can then be transferred onto the silicon surface. Again, computer aided design (CAD) tools assist layout designers in the task of translating the discrete circuit elements into shapes which will embody the devices themselves in the completed IC. These shapes make up the individual components of the circuit, such as gate electrodes, field oxidation regions, diffusion regions, metal interconnections, and so on.
The software programs employed by these CAD systems are usually structured to function under a set of predetermined design rules in order to produce a functional circuit. Often, these rules are determined by certain processing and design limitations. For example, design rules may define the space tolerance between devices or interconnect lines so as to ensure that the devices or lines do not interact with one another in any unwanted manner. Design rule limitations are frequently referred to as critical dimensions. A critical dimension of a circuit is commonly defined as the smallest width of a line or the smallest space between two lines. Consequently, the critical dimension determines the overall size and density of the IC. In present IC technology, the smallest critical dimension for commercial circuits is approximately 0.25 microns for line widths and spacings.
Once the layout of the circuit has been created, the next step to manufacturing the integrated circuit (IC) is to transfer the layout onto a semiconductor substrate. Optical lithography is a well known process for transferring geometric shapes onto the surface of a silicon wafer. The optical lithography process generally begins with the formation of a photoresist layer on the top surface of a semiconductor wafer. A mask having fully light non-transmissive opaque regions, which are usually formed of chrome, and fully light transmissive clear regions, which are usually formed of quartz, is then positioned over the photoresist coated wafer. Light is then shone on the mask via a visible light source or an ultra-violet light source. The light is focused to generate a reduced mask image on the wafer typically using an optical lens system which contains one or several lenses, filters, and or mirrors. This light passes through the clear regions of the mask to expose the underlying photoresist layer, and is blocked by the opaque regions of the mask, leaving that underlying portion of the photoresist layer unexposed. The exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor wafer coated with a photoresist layer exhibiting a desired pattern which defmes the geometries, features, lines and shapes of that layer. This pattern can then be used for etching underlying regions of the wafer.
Besides the aforementioned design rules, the resolution value of the exposure tool used in optical lithography also places limits on the designers of integrated circuit layouts. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose onto the wafer. Currently, the resolution for most advanced optical exposure tools is around 0.25 micron. As the critical dimensions of the layout become smaller and approach the resolution value of the lithography equipment, the consistency between the mask and the actual layout pattern developed in the photoresist is significantly reduced. Specifically, it is observed that differences in pattern development of circuit features depends upon the proximity of the features to one another.
With these limitations on IC design in mind, we note the data describing an IC pattern is usually represented in a condensed hierarchical fashion such as in a GDS-II data file. At the higher levels of pattern representation hierarchy, features are represented in a conceptual manner. For instance, a memory array may be described as having a given cell repeated for a certain number of rows and columns. The next lower level in the hierarchy might describe the basic memory cell, comprised of subcells A and B. Finally, at the lowest level, the most primitive subcells contain geometric primitives-rectangles and polygons. In order to generate a physical mask, the hierarchical data must first be flattened, enumerating every geometric instance described in the hierarchy. Flattening of the hierarchy typically results in several orders of magnitude increase in the size of data storage required to represent the pattern.
Since flattening the hierarchy results in such a large increase in the size of the file representing a given IC design, it is desirable to flatten the hierarchy at the latest point in the manufacture of a mask, which, in the best case, is at the time the mask design is loaded into the electron beam machine prior to physical manufacture. Currently however, this flattening process takes place at an earlier stage in the production of masks for some complicated IC""s. This is because the original mask design for a complicated IC is typically manipulated after the original design is completed in order to perform one of a number of operations on the design. These operations are performed because of the precision needed in the masks for complicated IC""s as the critical dimensions of these IC""s approach the resolution limits of optical lithography. Currently, these operations require some sort of flattening of the original design data in order to be performedxe2x80x94resulting in an earlier than desired flattening of the design data. These operations include the performance of logical operations, the generation of optical proximity corrections, the generation of phase shifting masks, and the design rule checking of masks that have undergone these operations.
In particular, nearly all modern integrated circuits of even limited complexity require that the original mask design be corrected for optical proximity effects in order that the desired image be accurately reproduced on a wafer after photolithography. Proximity effects occur when very closely spaced pattern features are lithographically transferred to a resist layer on a wafer. The light waves passing through the closely spaced features interact and, as a result, distort the final transferred pattern features. Another problem that occurs when feature sizes and spacing approach the resolution limit of the lithographic tool is that corners (concave and convex) tend to overexpose or underexpose due to a concentration or scarcity of energy at each of the corners. Other types of problems, such as over- or under-exposure of small features when large and small features are transferred from the same mask pattern, also occur.
Numerous methods have been developed to overcome the proximity effect problem. These methods include: precompensating mask line widths, varying photoresist layer thicknesses, using multi-layer photoresist processes, using electron beam imaging in conjunction with optical imaging, and finally, adding additional features to the original mask pattern to compensate for proximity effects. This last method is known as xe2x80x9cOptical Proximity Correctionxe2x80x9d (OPC).
The additional features that are added to the original mask when OPC is utilized are typically sub-resolution (i.e. have dimensions less than the resolution of the exposure tool) and thus do not transfer to the resist layer. Instead, they interact with the original pattern so as to improve the final transferred pattern and compensate for proximity effects.
Currently there are several known OPC software implemented products available that adjust mask definitions to include OPC features. However, thus far, the available products have a number of limitations in terms of correctness, speed, data volume, and verification of the resultant OPC corrected mask design.
One problem associated with OPC is that design rule checkers have difficulty determining whether the OPC corrected design conforms to the design rules. OPC typically introduces numerous serifs that cause the number of vertices in the design to increase tremendously. As the number of vertices increase, the amount of time required to perform design rule checking increases. Therefore, it is desirable to perform the design rule checking on OPC corrected designs more efficiently.
Therefore, what is desired is a method and apparatus for checking OPC corrected integrated circuit mask designs that solves the aforementioned problems.
One embodiment of the invention includes a method for performing design rule checking on OPC corrected or otherwise corrected designs. This method comprises accessing a corrected design and generating a simulated image. The simulated image corresponds to a simulation of an image which would be printed on a wafer if the wafer were exposed to an illumination source directed through the corrected design. The characteristics of the illumination source are determined by a set of lithography parameters. In creating the image, additional characteristics can be used to simulate portions of the fabrication process. However, what is important is that a resulting simulated image is created. The simulated image can then be used by the design rule checker. Importantly, the simulated image can be processed to reduce the number of vertices in the simulated image, relative to the number of vertices in the OPC corrected design layout.
In some embodiments, the hierarchy in the corrected design is maintained throughout the process. This allows for a more efficient creation of the simulated image and the design rule checking process.
In other embodiments, a method of adding corrections to a design is described. In these embodiments, a simulated image is compared with the desired design. Design rule errors identified in the comparison can then be used to add corrections to the original design (e.g., by adding OPC type corrections). In some embodiments, the hierarchy of the design can be maintained, thereby increasing the efficiency of the system.
Other embodiments are capable of checking all advanced masks such as OPC, PSM, and their derivatives, at a single process layer, and enables inter-layer dependence checking on the global process between individual mask layers. This embodiment begins by scanning through all patterns on the original mask design (also referred to as the ideal layout), and incorporating the newly corrected mask patterns (also referred to as the corrected layout) by simulating the aerial image intensity of the corrected mask at all locations. Aerial image simulation provides information about how the projected mask pattern will print when the physical mask is used in a photolithography stepper. Simulation of the aerial image can be reinforced by simulation of the resist and etch process to provide additional predictive accuracy. The simulation process provides quantitative information on both relative and absolute deviations of the simulated intensity edges or photoresist edges from the ideal layout.
The following heuristic describes this embodiment""s checking process. If the corrected layout is xe2x80x9ccorrectxe2x80x9d, the resulting intensity edge from lithography simulation deviates within a given distance from the ideal layout""s edge. On the other hand, if the all edge deviations between the ideal layout and the stepper intensity image of the corrected layout are within a given set of tolerances, the corrected layout can be considered xe2x80x9ccorrectxe2x80x9d.
There are several further applications based on the edge-checking technique. The geometry of the printed patterns from the corrected layout can now be conveniently generated in a format (e.g., GDS-II layout format) suitable for input to the conventional design rule checker, and this thus solves the problem of inter-layer dependence checking. In addition, this checking ability makes optical proximity corrections simple in two ways: First, if the corrected layout is identical to the ideal layout when the above-described checking is applied, by flagging the areas where the simulated edges deviate from the ideal layout, areas where corrections (e.g., OPC) are needed become immediately apparent. Second, by iteratively checking the intermediate design corrections against the ideal layout, this provides an efficient and flawless way for automated corrections (e.g., OPC).
In one embodiment, the simulation of a designed mask generates a designed image, which is compared against a physical image. The designed image is the image generated from the corrected layout (or other original mask layout). The physical image is an aerial image simulation that is generated from a physical mask picture. The picture of the physical mask is taken using a microscope, for example. The physical mask picture is, in one embodiment, a gray scale digital image of the physical mask. The physical image can then be generated using the same simulation techniques to generate the designed image. The designed image can then be compared against the physical image. The results of the comparison indicate whether the physical mask will generate the same structures as the designed mask would generate.
In one embodiment, these techniques are executed on a computer using software. In various embodiments, the computer is a Sun workstation, a personal computer running Windows NT, for example. The input of the ideal layout is in a file format such as GDS-II, but other embodiments use other layout description formats and languages.
Although many details have been included in the description and the figures, the invention is defined by the scope of the claims. Only limitations found in those claims apply to the invention.